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Items where Subject is "H612 Integrated Circuit Design"

JACS Subject (14)
- H Engineering (14)
  - H612 Integrated Circuit Design (14)

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0544:Electrical engineering 0984:Computer science Application software Applied sciences Automatic control Automation BCH codes Bayesian methods Bayesian networks Bio-medical imaging Boolean functions Boolean logic Bose Chaudhuri Hocquenghem codes CMOS Active Pixel Sensors CMOS cryptographic circuit security CMOS imagers CMOS integrated circuits CMOS logic circuits CMOS memory circuits CMOS technology Circuit synthesis Clocks Computer aided instruction Computer architecture Computer science Computer science education Design methodology Educational technology Electrical engineering Error correction codes Error modeling Fault tolerance Hamming codes ISCAS'85 benchmark circuit synthesis Instruments Integrated circuit modeling LUT-based Boolean logic approach Logic circuits Logic design Logic devices Logic functions Mammography Manufacturing Military computing NotOAChecked Permission Polarization Power demand Power dissipation Probabilistic modeling Probability distribution Pulse inverters QCA QCA circuit design QCA circuits QCA cryptographic circuits QCA logic design QCAPro Quantum cellular automata Quantum computing Quantum dots Quantum mechanics Quantum-dot cellular automata Reticle stitching S-box Serpent cipher Serpent submodule Switching circuits Tagging Upper bound Wafer scale sensors bad line exclusion technique belief networks bmjnyp cellular automata circuit reliability clock energy clocked QCA circuit clocked QCA circuits cryptography decryption process defect tolerance digital designs don't care conditions encryption process error analysis error correcting codes error correction codes error power estimation error-power tradeoffs fault rate tolerance techniques fault tolerance graphical probabilistic model ground states hybrid CMOS-nanoarchitecture hybrid nano-CMOS computational architecture hybrid nano/CMOS hybrid nano/CMOS computing architecture hybrid nanoCMOS architecture identification technology integrated circuit design integrated circuit reliability kink energy leakage power logic circuit logic circuits logic design logic functions logic gates logically reversible QCA circuit design look-up tables lookup table lookup-table low power consumption maximum kink energy nanoelectronics network synthesis non-adiabatic switching power loss nonadiabatic energy dissipation polarization error estimation polarization errors power analysis attack power dissipation power loss probabilistic automata probabilistic modeling scheme probabilistic modeling tool proton therapy quantum computing quantum dot cellular automata quantum dots quantum-dot cellular automata quantum-dot cellular automata (QCA) quantum-dot cellular automata (QCA) power model quantum-dot cellular automata technology reliability repair technique repair techniques sequential circuit design sequential circuits side channel attacks switching power table lookup tagged repair tagging mechanism thermal hot spots upper bound estimation upper bound power model

Number of items at this level: 192.

0544:Electrical engineering

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

0984:Computer science

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Application software

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Applied sciences

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Automatic control

Automation

BCH codes

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Bayesian methods

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Bayesian networks

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Bio-medical imaging

Esposito, Michela, Anaxagoras, Thalis, Zheng, Y., Speller, Robert, Evans, Philip, Allinson, Nigel and Wells, Kevin (2014) Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging. Physics in Medicine and Biology, 59 (13). pp. 3533-3554. ISSN 0031-9155

Boolean functions

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Boolean logic

Bose Chaudhuri Hocquenghem codes

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

CMOS Active Pixel Sensors

CMOS cryptographic circuit security

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

CMOS imagers

Esposito, Michela, Price, Tony, Manger, Sam, Waltham, Chris, Anaxagoras, Thalis, Parker, David, Nieto-Camero, Jaine and Allinson, Nigel (2016) A large area CMOS Active Pixel Sensor for imaging in proton therapy. Journal of Instrumentation, 13 . ISSN 1748-0221

CMOS integrated circuits

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

CMOS logic circuits

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

CMOS memory circuits

CMOS technology

Circuit synthesis

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Clocks

Computer aided instruction

Computer architecture

Computer science

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Computer science education

Design methodology

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Educational technology

Electrical engineering

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Error correction codes

Error modeling

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Fault tolerance

Hamming codes

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

ISCAS'85 benchmark circuit synthesis

Instruments

Integrated circuit modeling

LUT-based Boolean logic approach

Logic circuits

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Logic design

Logic devices

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Logic functions

Mammography

Manufacturing

Military computing

NotOAChecked

Permission

Polarization

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Power demand

Power dissipation

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, Saket, Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Probabilistic modeling

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Probability distribution

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Pulse inverters

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

QCA

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

QCA circuit design

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

QCA circuits

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

QCA cryptographic circuits

QCA logic design

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

QCAPro

Quantum cellular automata

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Quantum computing

Quantum dots

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Quantum mechanics

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Quantum-dot cellular automata

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Reticle stitching

S-box

Serpent cipher

Serpent submodule

Switching circuits

Tagging

Upper bound

Wafer scale sensors

bad line exclusion technique

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

belief networks

bmjnyp

cellular automata

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

circuit reliability

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

clock energy

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

clocked QCA circuit

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

clocked QCA circuits

cryptography

decryption process

defect tolerance

digital designs

don't care conditions

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

encryption process

error analysis

error correcting codes

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

error correction codes

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

error power estimation

error-power tradeoffs

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

fault rate tolerance techniques

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

fault tolerance

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

graphical probabilistic model

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

ground states

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

hybrid CMOS-nanoarchitecture

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

hybrid nano-CMOS computational architecture

hybrid nano/CMOS

hybrid nano/CMOS computing architecture

hybrid nanoCMOS architecture

identification technology

integrated circuit design

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

integrated circuit reliability

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

kink energy

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

leakage power

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

logic circuit

logic circuits

logic design

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

logic functions

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

logic gates

logically reversible QCA circuit design

look-up tables

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

lookup table

lookup-table

low power consumption

maximum kink energy

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

nanoelectronics

network synthesis

non-adiabatic switching power loss

nonadiabatic energy dissipation

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

polarization error estimation

polarization errors

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

power analysis attack

power dissipation

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

power loss

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

probabilistic automata

probabilistic modeling scheme

probabilistic modeling tool

proton therapy

quantum computing

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

quantum dot cellular automata

quantum dots

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

quantum-dot cellular automata

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

quantum-dot cellular automata (QCA)

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

quantum-dot cellular automata (QCA) power model

quantum-dot cellular automata technology

reliability

repair technique

repair techniques

sequential circuit design

sequential circuits

side channel attacks

switching power

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

table lookup

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

tagged repair

tagging mechanism

thermal hot spots

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

upper bound estimation

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

upper bound power model

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