Items where Subject is "H611 Microelectronic Engineering"

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Ab initio calculations Amorphous networks Amorphous silica Application software Atoms Automatic control Automation BCH codes Bayesian methods Bayesian network Bayesian networks Boolean functions Boolean logic Bose Chaudhuri Hocquenghem codes Buildings CFD CMOS cryptographic circuit security CMOS image sensors CMOS integrated circuits CMOS logic circuits CMOS memory circuits CMOS process CMOS technology Calculations Character recognition Charge transfer defects Circuit synthesis Circuit testing Classical potentials Clocks Complementary metal-oxide semiconductor devices Computational fluid dynamics Computational modelling Computational studies Computer aided instruction Computer architecture Computer science Computer science education Cryptography DFT Deep state traps Defects Density functional theory Design methodology Device reliability Educational technology Electron transfer Electron trapping Electron trapping sites Electron traps Electronic structure Energy gap Error correction codes Fault tolerance Flows in micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS) Gain measurement Geometrical and electronic structures Hamming codes Heat Transfer Hole traps Hydrogen bonds Hydroxyl E' center ISCAS'85 benchmark circuit synthesis Instruments Integrated circuit manufacture Integrated circuit modeling Interatomic potential Interfaces (materials) JCNotOpen K-map based knowledge modules LUT-based Boolean logic approach Logic circuits Logic design Logic devices Logic functions Logic gates MOS devices Manufacturing Micro- and nano- scale flow phenomena Microchannel Microchannel Cooling Military computing Nanoscale devices Negatively charged Neutral E' centres Noise level Noise measurement Noise reduction Permission Point defects Polarization Positively charged Power demand Power dissipation Power model Probability distribution Protons Pulse inverters QCA circuit design QCA circuits QCA computing QCA cryptographic circuits QCA logic design QCA macromodel. QCAPro Quantum cellular automata Quantum computing Quantum dots Quantum mechanics Quantum-dot cellular automata Rectangular S-box Sampling methods Security Architecture Semiconducting silicon Semiconductor devices Sensor arrays Sensor phenomena and characterization Sequential machines, Power analysis attack Serpent cipher Serpent cipher, Electric network analysis Serpent submodule Si-H bonds Si/SiO2 interface Silica Silicon Silicon oxides, Ab initio calculations Silicon oxides, Amorphous silicon Silicon, Amorphous silicon Switching circuits Tagging Total energy differences, Amorphous silicon Trapped electrons, Calculations Unpaired electrons, Charge transfer Upper bound bad line exclusion technique bayesian networks belief networks cellular automata circuit reliability circuit thermal behavior clock energy clocked QCA circuit clocked QCA circuits computer science education conditional probability characterization cryptography decryption process defect tolerance digital designs don't care conditions electronic engineering education encryption process error analysis error correcting codes error correction codes error power estimation error-power tradeoffs fault rate tolerance techniques fault tolerance fundamental abstracted logical behaviors future nanodevices graphical probabilistic model ground state probability inference ground states hierarchical probabilistic macromodeling hybrid CMOS-nanoarchitecture hybrid nano-CMOS computational architecture hybrid nano/CMOS hybrid nano/CMOS computing architecture hybrid nanoCMOS architecture identification technology integrated circuit design integrated circuit modelling integrated circuit reliability joint probability distribution kink energy leakage power logic circuit logic circuits logic design logic element macromodels logic functions logic gates logic synthesis logically reversible QCA circuit design look-up tables lookup table lookup-table low power consumption macromodel-based circuit level representation maximum kink energy nanoelectronics network synthesis non-adiabatic switching power loss nonadiabatic energy dissipation novel nanologic design concepts polarization error estimation polarization errors power analysis attack power dissipation power loss probabilistic automata probabilistic computing probabilistic modeling scheme probabilistic modeling tool probability quantum computing quantum dot cellular automata quantum dots quantum-dot cellular automata quantum-dot cellular automata (QCA) quantum-dot cellular automata (QCA) power model quantum-dot cellular automata technology rectangular microchannel reliability repair technique repair techniques scaling effect semiconductor quantum dots sequential circuit design sequential circuits side channel attacks standard CS courses standard EE courses students motivation switching power table lookup tagged repair tagging mechanism thermal hot spots thermal resistance. undergraduate logic design course upper bound estimation upper bound power model
Number of items at this level: 313.

Ab initio calculations

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

Amorphous networks

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Amorphous silica

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew B., Afanas’ev, V.V. and Shluger, Alexander L. (2013) A computational study of Si–H bonds as precursors for neutral E' centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Application software

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Atoms

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Automatic control

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Automation

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

BCH codes

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Bayesian methods

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Bayesian network

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Bayesian networks

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Boolean functions

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Boolean logic

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Bose Chaudhuri Hocquenghem codes

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Buildings

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

CFD

Yao, J., Yao, Y. F., Patel, M. K. and Mason, P. J. (2006) Numerical simulation of heat transfer in rectangular microchannel. In: European Conference on Computational Fluid Dynamics (ECCOMAS), September 5, 2006, Egmond aan Zee, The Netherlands.

Yao, Jun, Yao, Y.F., Patel, M. K. and Mason, P. J. (2006) Numerical simulation of microchannel cooling and heat transfer. In: 13th International Heat Transfer Conference, August 13, 2006, Sydney, Australia.

CMOS cryptographic circuit security

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

CMOS image sensors

Anaxagoras, Thalis, Kent, Paul, Allinson, Nigel, Turchetta, Renato, Pickering, Tim, Maneuski, Dzmitry, Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). pp. 2163-2175. ISSN 0018-9383

CMOS integrated circuits

Liu, Weiqiang, Srivastava, Saket, O'Neill, Maire and Swartzlander Jr., Earl E. (2014) Security issues in QCA circuit design: power analysis attacks. In: Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives. Springer Verlag, Tampa, FL, pp. 194-222. ISBN 9783662437216, 9783662437223

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

CMOS logic circuits

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

CMOS memory circuits

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

CMOS process

Anaxagoras, Thalis, Kent, Paul, Allinson, Nigel, Turchetta, Renato, Pickering, Tim, Maneuski, Dzmitry, Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). pp. 2163-2175. ISSN 0018-9383

CMOS technology

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Calculations

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Character recognition

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Charge transfer defects

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew B., Afanas’ev, V.V. and Shluger, Alexander L. (2013) A computational study of Si–H bonds as precursors for neutral E' centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Circuit synthesis

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Circuit testing

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Classical potentials

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

Clocks

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Liu, Weiqiang, Srivastava, Saket, O'Neill, Maire and Swartzlander Jr., Earl E. (2014) Security issues in QCA circuit design: power analysis attacks. In: Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives. Springer Verlag, Tampa, FL, pp. 194-222. ISBN 9783662437216, 9783662437223

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Complementary metal-oxide semiconductor devices

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Computational fluid dynamics

Yao, Jun, Yao, Yufeng, Mason, Peter J. and Patel, Mayur K. (2009) Numerical simulation of heat transfer in rectangular microchannel. Journal of Advances in Applied Mathematics and Mechanics, 1 (2). pp. 231-241. ISSN 2070-0733

Computational modelling

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Computational studies

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Computer aided instruction

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Computer architecture

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Computer science

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Computer science education

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Cryptography

Liu, Weiqiang, Srivastava, Saket, O'Neill, Maire and Swartzlander Jr., Earl E. (2014) Security issues in QCA circuit design: power analysis attacks. In: Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives. Springer Verlag, Tampa, FL, pp. 194-222. ISBN 9783662437216, 9783662437223

DFT

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew B., Afanas’ev, V.V. and Shluger, Alexander L. (2013) A computational study of Si–H bonds as precursors for neutral E' centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Deep state traps

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

Defects

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Density functional theory

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

Design methodology

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Device reliability

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew B., Afanas’ev, V.V. and Shluger, Alexander L. (2013) A computational study of Si–H bonds as precursors for neutral E' centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Educational technology

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Electron transfer

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Electron trapping

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

Electron trapping sites

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

Electron traps

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

Electronic structure

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

Energy gap

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

Error correction codes

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Fault tolerance

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Flows in micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS)

Yao, J., Yao, Y., Patel, M. K. and Mason, P. J. (2007) On Reynolds number and scaling effects in microchannel flows. The European Physical Journal - Applied Physics, 37 (2). pp. 229-235. ISSN 1286-0042

Gain measurement

Anaxagoras, Thalis, Kent, Paul, Allinson, Nigel, Turchetta, Renato, Pickering, Tim, Maneuski, Dzmitry, Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). pp. 2163-2175. ISSN 0018-9383

Geometrical and electronic structures

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

Hamming codes

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Heat Transfer

Yao, J., Yao, Y. F., Patel, M. K. and Mason, P. J. (2006) Numerical simulation of heat transfer in rectangular microchannel. In: European Conference on Computational Fluid Dynamics (ECCOMAS), September 5, 2006, Egmond aan Zee, The Netherlands.

Yao, Jun, Yao, Y.F., Patel, M. K. and Mason, P. J. (2006) Numerical simulation of microchannel cooling and heat transfer. In: 13th International Heat Transfer Conference, August 13, 2006, Sydney, Australia.

Hole traps

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Hydrogen bonds

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Hydroxyl E' center

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

ISCAS'85 benchmark circuit synthesis

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Instruments

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Integrated circuit manufacture

Liu, Weiqiang, Srivastava, Saket, O'Neill, Maire and Swartzlander Jr., Earl E. (2014) Security issues in QCA circuit design: power analysis attacks. In: Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives. Springer Verlag, Tampa, FL, pp. 194-222. ISBN 9783662437216, 9783662437223

Integrated circuit modeling

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Interatomic potential

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Interfaces (materials)

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

JCNotOpen

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

K-map based knowledge modules

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

LUT-based Boolean logic approach

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Logic circuits

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Logic design

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Logic devices

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Logic functions

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Logic gates

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

MOS devices

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Manufacturing

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Micro- and nano- scale flow phenomena

Yao, J., Yao, Y., Patel, M. K. and Mason, P. J. (2007) On Reynolds number and scaling effects in microchannel flows. The European Physical Journal - Applied Physics, 37 (2). pp. 229-235. ISSN 1286-0042

Microchannel

Yao, J., Yao, Y. F., Patel, M. K. and Mason, P. J. (2006) Numerical simulation of heat transfer in rectangular microchannel. In: European Conference on Computational Fluid Dynamics (ECCOMAS), September 5, 2006, Egmond aan Zee, The Netherlands.

Microchannel Cooling

Yao, Jun, Yao, Y.F., Patel, M. K. and Mason, P. J. (2006) Numerical simulation of microchannel cooling and heat transfer. In: 13th International Heat Transfer Conference, August 13, 2006, Sydney, Australia.

Military computing

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Nanoscale devices

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Negatively charged

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Neutral E' centres

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew B., Afanas’ev, V.V. and Shluger, Alexander L. (2013) A computational study of Si–H bonds as precursors for neutral E' centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Noise level

Anaxagoras, Thalis, Kent, Paul, Allinson, Nigel, Turchetta, Renato, Pickering, Tim, Maneuski, Dzmitry, Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). pp. 2163-2175. ISSN 0018-9383

Noise measurement

Anaxagoras, Thalis, Kent, Paul, Allinson, Nigel, Turchetta, Renato, Pickering, Tim, Maneuski, Dzmitry, Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). pp. 2163-2175. ISSN 0018-9383

Noise reduction

Anaxagoras, Thalis, Kent, Paul, Allinson, Nigel, Turchetta, Renato, Pickering, Tim, Maneuski, Dzmitry, Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). pp. 2163-2175. ISSN 0018-9383

Permission

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Point defects

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Polarization

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Positively charged

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Power demand

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Power dissipation

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, Saket, Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Power model

Liu, Weiqiang, Srivastava, Saket, O'Neill, Maire and Swartzlander Jr., Earl E. (2014) Security issues in QCA circuit design: power analysis attacks. In: Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives. Springer Verlag, Tampa, FL, pp. 194-222. ISBN 9783662437216, 9783662437223

Probability distribution

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Protons

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Pulse inverters

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

QCA circuit design

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

QCA circuits

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

QCA computing

Bhanja, Sanjukta and Srivastava, Saket (2005) Bayesian modeling of quantum-dot-cellular-automata circuits. In: NSTI Nanotechnology Conference 2005e, 8 - 12 May 2005, Anaheim.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

QCA cryptographic circuits

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

QCA logic design

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

QCA macromodel.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

QCAPro

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Quantum cellular automata

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, Saket, Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Quantum computing

Srivastava, Saket, Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Quantum dots

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, Saket, Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Quantum mechanics

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Quantum-dot cellular automata

Liu, Weiqiang, Srivastava, Saket, O'Neill, Maire and Swartzlander Jr., Earl E. (2014) Security issues in QCA circuit design: power analysis attacks. In: Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives. Springer Verlag, Tampa, FL, pp. 194-222. ISBN 9783662437216, 9783662437223

Rectangular

Yao, J., Yao, Y. F., Patel, M. K. and Mason, P. J. (2006) Numerical simulation of heat transfer in rectangular microchannel. In: European Conference on Computational Fluid Dynamics (ECCOMAS), September 5, 2006, Egmond aan Zee, The Netherlands.

S-box

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Liu, Weiqiang, Srivastava, Saket, O'Neill, Maire and Swartzlander Jr., Earl E. (2014) Security issues in QCA circuit design: power analysis attacks. In: Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives. Springer Verlag, Tampa, FL, pp. 194-222. ISBN 9783662437216, 9783662437223

Sampling methods

Anaxagoras, Thalis, Kent, Paul, Allinson, Nigel, Turchetta, Renato, Pickering, Tim, Maneuski, Dzmitry, Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). pp. 2163-2175. ISSN 0018-9383

Security Architecture

Liu, Weiqiang, Srivastava, Saket, O'Neill, Maire and Swartzlander Jr., Earl E. (2014) Security issues in QCA circuit design: power analysis attacks. In: Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives. Springer Verlag, Tampa, FL, pp. 194-222. ISBN 9783662437216, 9783662437223

Semiconducting silicon

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Semiconductor devices

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Sensor arrays

Anaxagoras, Thalis, Kent, Paul, Allinson, Nigel, Turchetta, Renato, Pickering, Tim, Maneuski, Dzmitry, Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). pp. 2163-2175. ISSN 0018-9383

Sensor phenomena and characterization

Anaxagoras, Thalis, Kent, Paul, Allinson, Nigel, Turchetta, Renato, Pickering, Tim, Maneuski, Dzmitry, Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). pp. 2163-2175. ISSN 0018-9383

Sequential machines, Power analysis attack

Liu, Weiqiang, Srivastava, Saket, O'Neill, Maire and Swartzlander Jr., Earl E. (2014) Security issues in QCA circuit design: power analysis attacks. In: Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives. Springer Verlag, Tampa, FL, pp. 194-222. ISBN 9783662437216, 9783662437223

Serpent cipher

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Serpent cipher, Electric network analysis

Liu, Weiqiang, Srivastava, Saket, O'Neill, Maire and Swartzlander Jr., Earl E. (2014) Security issues in QCA circuit design: power analysis attacks. In: Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives. Springer Verlag, Tampa, FL, pp. 194-222. ISBN 9783662437216, 9783662437223

Serpent submodule

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Si-H bonds

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew B., Afanas’ev, V.V. and Shluger, Alexander L. (2013) A computational study of Si–H bonds as precursors for neutral E' centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Si/SiO2 interface

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew B., Afanas’ev, V.V. and Shluger, Alexander L. (2013) A computational study of Si–H bonds as precursors for neutral E' centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Silica

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Silicon

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Silicon oxides, Ab initio calculations

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Silicon oxides, Amorphous silicon

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Silicon, Amorphous silicon

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

Switching circuits

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Tagging

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Total energy differences, Amorphous silicon

El-Sayed, Al-Moatasem, Watkins, Matthew B., Grasser, Tibor, Afanas'ev, Valeri V. and Shluger, Alexander L. (2015) Hole trapping at hydrogenic defects in amorphous silicon dioxide. Microelectronic Engineering, 147 . pp. 141-144. ISSN 0167-9317

Trapped electrons, Calculations

El-Sayed, Al-Moatasem, Watkins, Matthew, Shluger, Alexander L. and Afanas'ev, Valeri V. (2013) Identification of intrinsic electron trapping sites in bulk amorphous silica from ab initio calculations. Microelectronic Engineering, 109 . pp. 68-71. ISSN 0167-9317

Unpaired electrons, Charge transfer

Ling, Sanliang, El-Sayed, Al-Moatasem, Lopez-Gejo, Francisco, Watkins, Matthew, Afanas'ev, V. V. and Shluger, Alexander L. (2013) A computational study of Si-H bonds as precursors for neutral E ′ centres in amorphous silica and at the Si/SiO2 interface. Microelectronic Engineering, 109 . pp. 310-313. ISSN 0167-9317

Upper bound

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, Saket, Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

bad line exclusion technique

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

bayesian networks

Bhanja, Sanjukta and Srivastava, Saket (2005) Bayesian modeling of quantum-dot-cellular-automata circuits. In: NSTI Nanotechnology Conference 2005e, 8 - 12 May 2005, Anaheim.

belief networks

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

cellular automata

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

circuit reliability

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

circuit thermal behavior

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

clock energy

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

clocked QCA circuit

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

clocked QCA circuits

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

computer science education

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

conditional probability characterization

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

cryptography

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

decryption process

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

defect tolerance

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

digital designs

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

don't care conditions

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

electronic engineering education

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

encryption process

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

error analysis

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

error correcting codes

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

error correction codes

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

error power estimation

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

error-power tradeoffs

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

fault rate tolerance techniques

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

fault tolerance

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

fundamental abstracted logical behaviors

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

future nanodevices

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

graphical probabilistic model

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

ground state probability inference

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

ground states

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

hierarchical probabilistic macromodeling

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

hybrid CMOS-nanoarchitecture

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

hybrid nano-CMOS computational architecture

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

hybrid nano/CMOS

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

hybrid nano/CMOS computing architecture

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

hybrid nanoCMOS architecture

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

identification technology

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

integrated circuit design

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

integrated circuit modelling

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

integrated circuit reliability

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

joint probability distribution

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

kink energy

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

leakage power

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

logic circuit

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

logic circuits

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

logic design

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

logic element macromodels

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

logic functions

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

logic gates

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

logic synthesis

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

logically reversible QCA circuit design

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

look-up tables

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

lookup table

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

lookup-table

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

low power consumption

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

macromodel-based circuit level representation

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

maximum kink energy

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

nanoelectronics

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

network synthesis

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

non-adiabatic switching power loss

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

nonadiabatic energy dissipation

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

novel nanologic design concepts

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

polarization error estimation

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

polarization errors

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

power analysis attack

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

power dissipation

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

power loss

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

probabilistic automata

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

probabilistic computing

Bhanja, Sanjukta and Srivastava, Saket (2005) Bayesian modeling of quantum-dot-cellular-automata circuits. In: NSTI Nanotechnology Conference 2005e, 8 - 12 May 2005, Anaheim.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

probabilistic modeling scheme

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

probabilistic modeling tool

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

probability

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

quantum computing

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

quantum dot cellular automata

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

quantum dots

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S., Asthana, A., Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

quantum-dot cellular automata

Bhanja, Sanjukta and Srivastava, Saket (2005) Bayesian modeling of quantum-dot-cellular-automata circuits. In: NSTI Nanotechnology Conference 2005e, 8 - 12 May 2005, Anaheim.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S., Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

quantum-dot cellular automata (QCA)

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

quantum-dot cellular automata (QCA) power model

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

quantum-dot cellular automata technology

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

rectangular microchannel

Yao, Jun, Yao, Yufeng, Mason, Peter J. and Patel, Mayur K. (2009) Numerical simulation of heat transfer in rectangular microchannel. Journal of Advances in Applied Mathematics and Mechanics, 1 (2). pp. 231-241. ISSN 2070-0733

reliability

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

repair technique

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

repair techniques

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

scaling effect

Yao, Jun, Yao, Yufeng, Mason, Peter J. and Patel, Mayur K. (2009) Numerical simulation of heat transfer in rectangular microchannel. Journal of Advances in Applied Mathematics and Mechanics, 1 (2). pp. 231-241. ISSN 2070-0733

semiconductor quantum dots

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

sequential circuit design

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

sequential circuits

Venkataramani, P., Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

side channel attacks

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

standard CS courses

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

standard EE courses

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

students motivation

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

switching power

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

table lookup

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

tagged repair

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

tagging mechanism

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

thermal hot spots

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

thermal resistance.

Yao, Jun, Yao, Yufeng, Mason, Peter J. and Patel, Mayur K. (2009) Numerical simulation of heat transfer in rectangular microchannel. Journal of Advances in Applied Mathematics and Mechanics, 1 (2). pp. 231-241. ISSN 2070-0733

undergraduate logic design course

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

upper bound estimation

Srivastava, S., Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

upper bound power model

Liu, Weiqiang, Srivastava, Saket, Lu, Liang, O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

This list was generated on Wed May 25 10:24:45 2022 BST.