Realisation of a modified CMAC architecture using reconfigurable logic devices

Kolez, Aleksander and Allinson, Nigel (1993) Realisation of a modified CMAC architecture using reconfigurable logic devices. In: 3rd Workshop on Neural Networks: Academic/Industrial/NASA/Defense, 10-12 February 1992, Alabama, AL, USA.

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Item Type:Conference or Workshop contribution (Paper)
Item Status:Live Archive


The CMAC is a perception-like computational structure proposed originally by J. Albus in 1975. It is attractive for real-time applications, as it can be realised using conventional RAM, and the output computation involves the summation of a fixed (usually small) number of weights. The selection of weights is carried out by means of hash coding, which unfortunately introduces hashing collisions. A modification of the original architecture is proposed, which allows the elimination of intravector collisions arising when two or more variables of the same address vector (induced by a given input vector) map onto the same memory position. The improved method is based on a blocked rather than a continuous weight memory scheme. A project has been undertaken to find and efficient hardware implementation of the CMAC structure using programmable hardware (EPDLs and FPGAs) as building blocks. The CMAC has been realised as a single Xillnx FPGA device. The chip has been incorporated into an AT computer card to be used as a high speed hardware accelerator in CMAC applications.

Keywords:Codes (symbols), Computer hardware, Logic devices, Neural networks, RAM, Random access storage, CMAC architecture Reconfigurable logic devices, Computer architecture
Subjects:G Mathematical and Computer Sciences > G400 Computer Science
G Mathematical and Computer Sciences > G730 Neural Computing
G Mathematical and Computer Sciences > G740 Computer Vision
Divisions:College of Science > School of Computer Science
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ID Code:8613
Deposited On:31 May 2013 11:52

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