Howard, Neil J., Tyrrell, Andrew M. and Allinson, Nigel M.
(1996)
The use of field-programmable gate arrays for the hardware acceleration of design automation tasks.
VLSI Design, 4
(2).
pp. 135-139.
ISSN 1065-514X
Full content URL: http://www.hindawi.com/journals/vlsi/1996/017505/a...
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| Item Type: | Article |
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| Item Status: | Live Archive |
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Abstract
This paper investigates the possibility of using Field-Programmable Gate Arrays (Fr’GAS) as
reconfigurable co-processors for workstations to produce moderate speedups for most tasks
in the design process, resulting in a worthwhile overall design process speedup at low cost
and allowing algorithm upgrades with no hardware modification. The use of FPGAS as hardware
accelerators is reviewed and then achievable speedups are predicted for logic simulation
and VLSI design rule checking tasks for various FPGA co-processor arrangements.
| Additional Information: | This paper investigates the possibility of using Field-Programmable Gate Arrays (Fr’GAS) as
reconfigurable co-processors for workstations to produce moderate speedups for most tasks
in the design process, resulting in a worthwhile overall design process speedup at low cost
and allowing algorithm upgrades with no hardware modification. The use of FPGAS as hardware
accelerators is reviewed and then achievable speedups are predicted for logic simulation
and VLSI design rule checking tasks for various FPGA co-processor arrangements. |
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| Keywords: | Field-Programmable Gate Arrays, FPGA, Algorithm, oaopen |
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| Subjects: | G Mathematical and Computer Sciences > G730 Neural Computing |
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| Divisions: | College of Science > School of Computer Science |
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| ID Code: | 5029 |
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| Deposited On: | 20 Apr 2012 08:47 |
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