A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS

Zheng, X., Zhang, C., Lv, F. , Zhao, F., Yue, S., Wang, Z., Li, F., Jiang, H. and Wang, Z. (2017) A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. In: 38th Annual Custom Integrated Circuits Conference, CICC 2017, 30 April - 3 May 2017, Austin, TX, USA.

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Item Type:Conference or Workshop contribution (Paper)
Item Status:Live Archive


This paper presents a 4-40 Gb/s current mode PAM4 transmitter with an optimized eye linearity. By embedding an additional mixed combiner and an extra current source into the output driver and developing a coherent scaled-replica based bias generator, the channel-length modulation caused tail-current variations for both DC and AC coupling modes can be effectively compensated. Implemented in 65 nm CMOS, the transmitter occupies an area of 1.02 mm2 and consumes 102 mW at 40 Gb/s. After applying the proposed linearity optimization, the measured eye linearity can be optimized from 1.28 to 1.01 with a single-end swing of 480 mV in AC coupling mode. © 2017 IEEE.

Additional Information:Conference Code:129634
Keywords:CMOS integrated circuits, Integrated circuit manufacture, Transmitters, Bias generators, Channel length modulation, Current mode, Current sources, Linearity optimization, Output drivers, PAM4 transmitters, Tail currents, Pulse amplitude modulation
Divisions:College of Science > School of Computer Science
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ID Code:29189
Deposited On:02 Nov 2017 15:17

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