An S/H circuit with parasitics optimized for IF-sampling

Xuqiang, Zheng, Fule, Li, Zhijun, Wang , Weitao, Li, Wen, Jia, Zhihua, Wang and Yue, Shigang (2016) An S/H circuit with parasitics optimized for IF-sampling. Journal of Semiconductors, 37 (6). 065005. ISSN 1674-4926

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Item Type:Article
Item Status:Live Archive


An IF-sampling S/H is presented, which adopts a flip-around structure, bottom-plate sampling technique and improved input bootstrapped switches. To achieve high sampling linearity over a wide input frequency range, the floating well technique is utilized to optimize the input switches. Besides, techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance. The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit, 250 MS/s pipeline ADC. For 30 MHz input, the measured SFDR/SNDR of the ADC is 94.7 dB/68. 5dB, which can remain over 84.3 dB/65.4 dB for input frequency up to 400 MHz. The ADC presents excellent dynamic performance at high input frequency, which is mainly attributed to the parasitics optimized S/H circuit.

Keywords:Semiconductors, NotOAChecked
Subjects:G Mathematical and Computer Sciences > G400 Computer Science
H Engineering > H600 Electronic and Electrical Engineering
Divisions:College of Science > School of Computer Science
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ID Code:27940
Deposited On:11 Aug 2017 09:26

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