Repair techniques for hybrid Nano/CMOS computational architecture

Srivastava, S., Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

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Item Type:Conference or Workshop contribution (Poster)
Item Status:Live Archive


Presence of high defect rate in nanofabrics due to the inadequate fabrication processes has held back the development of emerging technology architecture. In this work, we propose two repair techniques to provide high level of defect tolerance in lookup table (LUT) based Boolean logic approach implemented in nano/CMOS. Further, we demonstrate that direct application of memory repair techniques is ineffective in dealing with high defect rate in hybrid nano/CMOS architecture. We show that the proposed techniques are capable of handling more than 20 defect rate in hybrid nano/CMOS architecture with efficient utilization of spare units.

Keywords:CMOS integrated circuits, nanoelectronics, defect tolerance, hybrid nano-CMOS computational architecture, CMOS logic circuits, CMOS memory circuits, Computer architecture, Error correction codes
Subjects:H Engineering > H611 Microelectronic Engineering
H Engineering > H620 Electrical Engineering
H Engineering > H651 Digital Circuit Engineering
H Engineering > H610 Electronic Engineering
H Engineering > H612 Integrated Circuit Design
Divisions:College of Science > School of Computer Science
College of Science > School of Engineering
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ID Code:10734
Deposited On:22 Jul 2013 09:51

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