Abstract

The goal of this work is to present a worst-case power estimation model for QCA designs. Based on existing power models, we derive upper bound for power dissipation that occurs for non-adiabatic clock switching and represents the worst-case power estimate. This upper bound is easy to compute and does not require simulation of quantum dynamics. Given the criticality of thermal issues and the inherent process variabilities at nano-scale, such worst case estimates, that is easy to compute, will be useful at higher levels of design abstractions, so as to vet different designs or to create power macromodels for different circuit components. There are three power dissipation events for each cell: first when the clock goes up, second when the input switches, and third when the clock goes down. The first and the third events are analogous to “leakage” power in CMOS designs in that there is dissipation even when there is no change in inputs. The second event can be related to “switching” power in CMOS and is dependent on inputs. The proportion between these two types of dissipations is strongly dependent on the clock energy. In addition to the clock, the other determining factors are cell polarization, kink energy, and quantum relaxation time. We demonstrate the model using majority gate and inverter, which are critical circuit components.