Items where Subject is "H Engineering > H612 Integrated Circuit Design"

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0544:Electrical engineering 0984:Computer science Application software Applied sciences Automatic control Automation BCH codes Bayesian methods Bayesian networks Bio-medical imaging Boolean functions Boolean logic Bose Chaudhuri Hocquenghem codes CMOS Active Pixel Sensors CMOS cryptographic circuit security CMOS imagers CMOS integrated circuits CMOS logic circuits CMOS memory circuits CMOS technology Circuit synthesis Clocks Computer aided instruction Computer architecture Computer science Computer science education Design methodology Educational technology Electrical engineering Error correction codes Error modeling Fault tolerance Hamming codes ISCAS'85 benchmark circuit synthesis Instruments Integrated circuit modeling LUT-based Boolean logic approach Logic circuits Logic design Logic devices Logic functions Mammography Manufacturing Military computing NotOAChecked Permission Polarization Power demand Power dissipation Probabilistic modeling Probability distribution Pulse inverters QCA QCA circuit design QCA circuits QCA cryptographic circuits QCA logic design QCAPro Quantum cellular automata Quantum computing Quantum dots Quantum mechanics Quantum-dot cellular automata Reticle stitching S-box Serpent cipher Serpent submodule Switching circuits Tagging Upper bound Wafer scale sensors bad line exclusion technique belief networks bmjnyp cellular automata circuit reliability clock energy clocked QCA circuit clocked QCA circuits cryptography decryption process defect tolerance digital designs don't care conditions encryption process error analysis error correcting codes error correction codes error power estimation error-power tradeoffs fault rate tolerance techniques fault tolerance graphical probabilistic model ground states hybrid CMOS-nanoarchitecture hybrid nano-CMOS computational architecture hybrid nano/CMOS hybrid nano/CMOS computing architecture hybrid nanoCMOS architecture identification technology integrated circuit design integrated circuit reliability kink energy leakage power logic circuit logic circuits logic design logic functions logic gates logically reversible QCA circuit design look-up tables lookup table lookup-table low power consumption maximum kink energy nanoelectronics network synthesis non-adiabatic switching power loss nonadiabatic energy dissipation polarization error estimation polarization errors power analysis attack power dissipation power loss probabilistic automata probabilistic modeling scheme probabilistic modeling tool proton therapy quantum computing quantum dot cellular automata quantum dots quantum-dot cellular automata quantum-dot cellular automata (QCA) quantum-dot cellular automata (QCA) power model quantum-dot cellular automata technology reliability repair technique repair techniques sequential circuit design sequential circuits side channel attacks switching power table lookup tagged repair tagging mechanism thermal hot spots upper bound estimation upper bound power model
Number of items at this level: 192.

0544:Electrical engineering

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

0984:Computer science

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Application software

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Applied sciences

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Automatic control

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Automation

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

BCH codes

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Bayesian methods

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Bayesian networks

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Bio-medical imaging

Esposito, Michela and Anaxagoras, Thalis and Zheng, Y. and Speller, Robert and Evans, Philip and Allinson, Nigel and Wells, Kevin (2014) Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging. Physics in Medicine and Biology, 59 (13). pp. 3533-3554. ISSN 0031-9155

Boolean functions

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Boolean logic

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Bose Chaudhuri Hocquenghem codes

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

CMOS Active Pixel Sensors

Esposito, Michela and Anaxagoras, Thalis and Zheng, Y. and Speller, Robert and Evans, Philip and Allinson, Nigel and Wells, Kevin (2014) Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging. Physics in Medicine and Biology, 59 (13). pp. 3533-3554. ISSN 0031-9155

CMOS cryptographic circuit security

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

CMOS imagers

Esposito, Michela and Price, Tony and Manger, Sam and Waltham, Chris and Anaxagoras, Thalis and Parker, David and Nieto-Camero, Jaine and Allinson, Nigel (2016) A large area CMOS Active Pixel Sensor for imaging in proton therapy. Journal of Instrumentation, 13 . ISSN 1748-0221

CMOS integrated circuits

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

CMOS logic circuits

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

CMOS memory circuits

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

CMOS technology

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Circuit synthesis

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Clocks

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Computer aided instruction

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Computer architecture

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Computer science

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Computer science education

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Design methodology

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Educational technology

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Electrical engineering

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Error correction codes

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Error modeling

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Fault tolerance

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Hamming codes

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

ISCAS'85 benchmark circuit synthesis

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Instruments

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Integrated circuit modeling

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

LUT-based Boolean logic approach

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Logic circuits

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Logic design

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Logic devices

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Logic functions

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Mammography

Esposito, Michela and Anaxagoras, Thalis and Zheng, Y. and Speller, Robert and Evans, Philip and Allinson, Nigel and Wells, Kevin (2014) Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging. Physics in Medicine and Biology, 59 (13). pp. 3533-3554. ISSN 0031-9155

Manufacturing

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Military computing

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

NotOAChecked

Esposito, Michela and Anaxagoras, Thalis and Zheng, Y. and Speller, Robert and Evans, Philip and Allinson, Nigel and Wells, Kevin (2014) Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging. Physics in Medicine and Biology, 59 (13). pp. 3533-3554. ISSN 0031-9155

Permission

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Polarization

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Power demand

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Power dissipation

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Srivastava, Saket and Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Probabilistic modeling

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Probability distribution

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Pulse inverters

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

QCA

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

QCA circuit design

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

QCA circuits

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

QCA cryptographic circuits

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

QCA logic design

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

QCAPro

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Quantum cellular automata

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, Saket and Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Quantum computing

Srivastava, Saket and Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Quantum dots

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, Saket and Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Quantum mechanics

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Quantum-dot cellular automata

Srivastava, Saket (2007) Probabilistic modeling of quantum-dot cellular automata. PhD thesis, University of South Florida.

Reticle stitching

Esposito, Michela and Anaxagoras, Thalis and Zheng, Y. and Speller, Robert and Evans, Philip and Allinson, Nigel and Wells, Kevin (2014) Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging. Physics in Medicine and Biology, 59 (13). pp. 3533-3554. ISSN 0031-9155

S-box

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Serpent cipher

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Serpent submodule

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Switching circuits

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Tagging

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Upper bound

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, Saket and Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Wafer scale sensors

Esposito, Michela and Anaxagoras, Thalis and Zheng, Y. and Speller, Robert and Evans, Philip and Allinson, Nigel and Wells, Kevin (2014) Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging. Physics in Medicine and Biology, 59 (13). pp. 3533-3554. ISSN 0031-9155

bad line exclusion technique

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

belief networks

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

bmjnyp

Esposito, Michela and Anaxagoras, Thalis and Zheng, Y. and Speller, Robert and Evans, Philip and Allinson, Nigel and Wells, Kevin (2014) Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging. Physics in Medicine and Biology, 59 (13). pp. 3533-3554. ISSN 0031-9155

cellular automata

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

circuit reliability

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

clock energy

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

clocked QCA circuit

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

clocked QCA circuits

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

cryptography

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

decryption process

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

defect tolerance

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

digital designs

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

don't care conditions

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

encryption process

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

error analysis

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

error correcting codes

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

error correction codes

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

error power estimation

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

error-power tradeoffs

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

fault rate tolerance techniques

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

fault tolerance

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

graphical probabilistic model

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

ground states

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

hybrid CMOS-nanoarchitecture

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

hybrid nano-CMOS computational architecture

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

hybrid nano/CMOS

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

hybrid nano/CMOS computing architecture

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

hybrid nanoCMOS architecture

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

identification technology

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

integrated circuit design

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

integrated circuit reliability

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

kink energy

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

leakage power

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

logic circuit

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

logic circuits

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

logic design

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

logic functions

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

logic gates

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

logically reversible QCA circuit design

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

look-up tables

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

lookup table

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

lookup-table

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

low power consumption

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

maximum kink energy

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

nanoelectronics

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

network synthesis

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

non-adiabatic switching power loss

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

nonadiabatic energy dissipation

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

polarization error estimation

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

polarization errors

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

power analysis attack

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

power dissipation

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

power loss

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

probabilistic automata

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

probabilistic modeling scheme

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

probabilistic modeling tool

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

proton therapy

Esposito, Michela and Price, Tony and Manger, Sam and Waltham, Chris and Anaxagoras, Thalis and Parker, David and Nieto-Camero, Jaine and Allinson, Nigel (2016) A large area CMOS Active Pixel Sensor for imaging in proton therapy. Journal of Instrumentation, 13 . ISSN 1748-0221

quantum computing

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

quantum dot cellular automata

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

quantum dots

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

quantum-dot cellular automata

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

quantum-dot cellular automata (QCA)

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

quantum-dot cellular automata (QCA) power model

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

quantum-dot cellular automata technology

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

reliability

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

repair technique

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

repair techniques

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

sequential circuit design

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

sequential circuits

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

side channel attacks

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

switching power

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

table lookup

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

tagged repair

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

tagging mechanism

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

thermal hot spots

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

upper bound estimation

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

upper bound power model

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

This list was generated on Sun Oct 13 21:00:12 2019 BST.