Items where Subject is "H Engineering > H611 Microelectronic Engineering"

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Application software Automatic control Automation BCH codes Bayesian methods Bayesian network Bayesian networks Boolean functions Boolean logic Bose Chaudhuri Hocquenghem codes Buildings CFD CMOS cryptographic circuit security CMOS image sensors CMOS integrated circuits CMOS logic circuits CMOS memory circuits CMOS process CMOS technology Character recognition Circuit synthesis Circuit testing Clocks Computational fluid dynamics Computer aided instruction Computer architecture Computer science Computer science education Design methodology Educational technology Error correction codes Fault tolerance Flows in micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS) Gain measurement Hamming codes Heat Transfer ISCAS'85 benchmark circuit synthesis Instruments Integrated circuit modeling K-map based knowledge modules LUT-based Boolean logic approach Logic circuits Logic design Logic devices Logic functions Logic gates Manufacturing Micro- and nano- scale flow phenomena Microchannel Microchannel Cooling Military computing Nanoscale devices Noise level Noise measurement Noise reduction Permission Polarization Power demand Power dissipation Probability distribution Pulse inverters QCA circuit design QCA circuits QCA computing QCA cryptographic circuits QCA logic design QCA macromodel. QCAPro Quantum cellular automata Quantum computing Quantum dots Quantum mechanics Rectangular S-box Sampling methods Sensor arrays Sensor phenomena and characterization Serpent cipher Serpent submodule Switching circuits Tagging Upper bound bad line exclusion technique belief networks cellular automata circuit reliability circuit thermal behavior clock energy clocked QCA circuit clocked QCA circuits computer science education conditional probability characterization cryptography decryption process defect tolerance digital designs don't care conditions electronic engineering education encryption process error analysis error correcting codes error correction codes error power estimation error-power tradeoffs fault rate tolerance techniques fault tolerance fundamental abstracted logical behaviors future nanodevices graphical probabilistic model ground state probability inference ground states hierarchical probabilistic macromodeling hybrid CMOS-nanoarchitecture hybrid nano-CMOS computational architecture hybrid nano/CMOS hybrid nano/CMOS computing architecture hybrid nanoCMOS architecture identification technology integrated circuit design integrated circuit modelling integrated circuit reliability joint probability distribution kink energy leakage power logic circuit logic circuits logic design logic element macromodels logic functions logic gates logic synthesis logically reversible QCA circuit design look-up tables lookup table lookup-table low power consumption macromodel-based circuit level representation maximum kink energy nanoelectronics network synthesis non-adiabatic switching power loss nonadiabatic energy dissipation novel nanologic design concepts polarization error estimation polarization errors power analysis attack power dissipation power loss probabilistic automata probabilistic computing probabilistic modeling scheme probabilistic modeling tool probability quantum computing quantum dot cellular automata quantum dots quantum-dot cellular automata quantum-dot cellular automata (QCA) quantum-dot cellular automata (QCA) power model quantum-dot cellular automata technology rectangular microchannel reliability repair technique repair techniques scaling effect semiconductor quantum dots sequential circuit design sequential circuits side channel attacks standard CS courses standard EE courses students motivation switching power table lookup tagged repair tagging mechanism thermal hot spots thermal resistance. undergraduate logic design course upper bound estimation upper bound power model
Number of items at this level: 244.

Application software

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Automatic control

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Automation

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

BCH codes

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Bayesian methods

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Bayesian network

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Bayesian networks

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Boolean functions

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Boolean logic

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Bose Chaudhuri Hocquenghem codes

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Buildings

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

CFD

Yao, J. and Yao, Y. F. and Patel, M. K. and Mason, P. J. (2006) Numerical simulation of heat transfer in rectangular microchannel. In: European Conference on Computational Fluid Dynamics (ECCOMAS), September 5, 2006, Egmond aan Zee, The Netherlands.

Yao, Jun and Yao, Y.F. and Patel, M. K. and Mason, P. J. (2006) Numerical simulation of microchannel cooling and heat transfer. In: 13th International Heat Transfer Conference, August 13, 2006, Sydney, Australia.

CMOS cryptographic circuit security

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

CMOS image sensors

Anaxagoras, Thalis and Kent, Paul and Allinson, Nigel and Turchetta, Renato and Pickering, Tim and Maneuski, Dzmitry and Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). 2163-2175 . ISSN 0018-9383

CMOS integrated circuits

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

CMOS logic circuits

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

CMOS memory circuits

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

CMOS process

Anaxagoras, Thalis and Kent, Paul and Allinson, Nigel and Turchetta, Renato and Pickering, Tim and Maneuski, Dzmitry and Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). 2163-2175 . ISSN 0018-9383

CMOS technology

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Character recognition

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Circuit synthesis

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Circuit testing

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Clocks

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Computational fluid dynamics

Yao, Jun and Yao, Yufeng and Mason, Peter J. and Patel, Mayur K. (2009) Numerical simulation of heat transfer in rectangular microchannel. Journal of Advances in Applied Mathematics and Mechanics, 1 (2). pp. 231-241. ISSN 2070-0733

Computer aided instruction

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Computer architecture

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Computer science

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Computer science education

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Design methodology

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Educational technology

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Error correction codes

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Fault tolerance

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Flows in micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS)

Yao, J. and Yao, Y. and Patel, M. K. and Mason, P. J. (2007) On Reynolds number and scaling effects in microchannel flows. The European Physical Journal - Applied Physics, 37 (2). pp. 229-235. ISSN 1286-0042

Gain measurement

Anaxagoras, Thalis and Kent, Paul and Allinson, Nigel and Turchetta, Renato and Pickering, Tim and Maneuski, Dzmitry and Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). 2163-2175 . ISSN 0018-9383

Hamming codes

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Heat Transfer

Yao, J. and Yao, Y. F. and Patel, M. K. and Mason, P. J. (2006) Numerical simulation of heat transfer in rectangular microchannel. In: European Conference on Computational Fluid Dynamics (ECCOMAS), September 5, 2006, Egmond aan Zee, The Netherlands.

Yao, Jun and Yao, Y.F. and Patel, M. K. and Mason, P. J. (2006) Numerical simulation of microchannel cooling and heat transfer. In: 13th International Heat Transfer Conference, August 13, 2006, Sydney, Australia.

ISCAS'85 benchmark circuit synthesis

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Instruments

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Integrated circuit modeling

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

K-map based knowledge modules

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

LUT-based Boolean logic approach

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Logic circuits

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Logic design

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Logic devices

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Logic functions

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Logic gates

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Manufacturing

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Micro- and nano- scale flow phenomena

Yao, J. and Yao, Y. and Patel, M. K. and Mason, P. J. (2007) On Reynolds number and scaling effects in microchannel flows. The European Physical Journal - Applied Physics, 37 (2). pp. 229-235. ISSN 1286-0042

Microchannel

Yao, J. and Yao, Y. F. and Patel, M. K. and Mason, P. J. (2006) Numerical simulation of heat transfer in rectangular microchannel. In: European Conference on Computational Fluid Dynamics (ECCOMAS), September 5, 2006, Egmond aan Zee, The Netherlands.

Microchannel Cooling

Yao, Jun and Yao, Y.F. and Patel, M. K. and Mason, P. J. (2006) Numerical simulation of microchannel cooling and heat transfer. In: 13th International Heat Transfer Conference, August 13, 2006, Sydney, Australia.

Military computing

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Nanoscale devices

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Noise level

Anaxagoras, Thalis and Kent, Paul and Allinson, Nigel and Turchetta, Renato and Pickering, Tim and Maneuski, Dzmitry and Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). 2163-2175 . ISSN 0018-9383

Noise measurement

Anaxagoras, Thalis and Kent, Paul and Allinson, Nigel and Turchetta, Renato and Pickering, Tim and Maneuski, Dzmitry and Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). 2163-2175 . ISSN 0018-9383

Noise reduction

Anaxagoras, Thalis and Kent, Paul and Allinson, Nigel and Turchetta, Renato and Pickering, Tim and Maneuski, Dzmitry and Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). 2163-2175 . ISSN 0018-9383

Permission

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Polarization

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Power demand

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Power dissipation

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, Saket and Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Probability distribution

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Pulse inverters

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

QCA circuit design

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

QCA circuits

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

QCA computing

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

QCA cryptographic circuits

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

QCA logic design

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

QCA macromodel.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

QCAPro

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Quantum cellular automata

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, Saket and Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Quantum computing

Srivastava, Saket and Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

Quantum dots

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, Saket and Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

Quantum mechanics

Srivastava, S. and Bhanja, S. (2006) Bayesian macromodeling for circuit level QCA design. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006.

Rectangular

Yao, J. and Yao, Y. F. and Patel, M. K. and Mason, P. J. (2006) Numerical simulation of heat transfer in rectangular microchannel. In: European Conference on Computational Fluid Dynamics (ECCOMAS), September 5, 2006, Egmond aan Zee, The Netherlands.

S-box

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Sampling methods

Anaxagoras, Thalis and Kent, Paul and Allinson, Nigel and Turchetta, Renato and Pickering, Tim and Maneuski, Dzmitry and Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). 2163-2175 . ISSN 0018-9383

Sensor arrays

Anaxagoras, Thalis and Kent, Paul and Allinson, Nigel and Turchetta, Renato and Pickering, Tim and Maneuski, Dzmitry and Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). 2163-2175 . ISSN 0018-9383

Sensor phenomena and characterization

Anaxagoras, Thalis and Kent, Paul and Allinson, Nigel and Turchetta, Renato and Pickering, Tim and Maneuski, Dzmitry and Blue, Andrew and O'Shea, Val (2010) eLeNA: a parametric CMOS active-pixel sensor for the evaluation of reset noise reduction architectures. IEEE Transactions on Electron Devices, 57 (9). 2163-2175 . ISSN 0018-9383

Serpent cipher

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Serpent submodule

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Switching circuits

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Tagging

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Upper bound

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, Saket and Sarkar, Sudeep and Bhanja, Sanjukta (2006) Power dissipation bounds and models for quantum-dot cellular automata circuits. In: Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 17-20 June 2006, Cinncinati, OH.

bad line exclusion technique

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

belief networks

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

cellular automata

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

circuit reliability

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

circuit thermal behavior

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

clock energy

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

clocked QCA circuit

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

clocked QCA circuits

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

computer science education

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

conditional probability characterization

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

cryptography

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

decryption process

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

defect tolerance

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

digital designs

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

don't care conditions

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

electronic engineering education

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

encryption process

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

error analysis

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

error correcting codes

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

error correction codes

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

error power estimation

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

error-power tradeoffs

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

fault rate tolerance techniques

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

fault tolerance

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

fundamental abstracted logical behaviors

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

future nanodevices

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

graphical probabilistic model

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

ground state probability inference

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

ground states

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

hierarchical probabilistic macromodeling

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

hybrid CMOS-nanoarchitecture

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

hybrid nano-CMOS computational architecture

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

hybrid nano/CMOS

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

hybrid nano/CMOS computing architecture

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

hybrid nanoCMOS architecture

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

identification technology

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

integrated circuit design

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

integrated circuit modelling

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

integrated circuit reliability

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

joint probability distribution

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

kink energy

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

leakage power

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

logic circuit

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

logic circuits

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

logic design

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

logic element macromodels

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

logic functions

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

logic gates

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

logic synthesis

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

logically reversible QCA circuit design

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

look-up tables

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

lookup table

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

lookup-table

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

low power consumption

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

macromodel-based circuit level representation

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

maximum kink energy

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

nanoelectronics

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Repair techniques for hybrid Nano/CMOS computational architecture. In: Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 26-30 July 2009, Genoa.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

network synthesis

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

non-adiabatic switching power loss

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

nonadiabatic energy dissipation

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

novel nanologic design concepts

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

polarization error estimation

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

polarization errors

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

power analysis attack

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

power dissipation

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

power loss

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

probabilistic automata

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

probabilistic computing

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

probabilistic modeling scheme

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

probabilistic modeling tool

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

probability

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

quantum computing

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

quantum dot cellular automata

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

quantum dots

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

Srivastava, S. and Asthana, A. and Bhanja, S. and Sarkar, S. (2011) QCAPro: an error-power estimation tool for QCA circuit design. In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 15-18 May 2011, Rio de Janeiro.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

quantum-dot cellular automata

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

Srivastava, S. and Sarkar, S. and Bhanja, S. (2008) Error-power tradeoffs in QCA design. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 August 2008, Arlington, TX.

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

quantum-dot cellular automata (QCA)

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

quantum-dot cellular automata (QCA) power model

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

quantum-dot cellular automata technology

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

rectangular microchannel

Yao, Jun and Yao, Yufeng and Mason, Peter J. and Patel, Mayur K. (2009) Numerical simulation of heat transfer in rectangular microchannel. Journal of Advances in Applied Mathematics and Mechanics, 1 (2). pp. 231-241. ISSN 2070-0733

reliability

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

repair technique

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

repair techniques

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

scaling effect

Yao, Jun and Yao, Yufeng and Mason, Peter J. and Patel, Mayur K. (2009) Numerical simulation of heat transfer in rectangular microchannel. Journal of Advances in Applied Mathematics and Mechanics, 1 (2). pp. 231-241. ISSN 2070-0733

semiconductor quantum dots

Srivastava, S. and Bhanja, S. (2007) Hierarchical probabilistic macromodeling for QCA circuits. Computers, IEEE Transactions on, 56 (2). pp. 174-190. ISSN 0018-9340

sequential circuit design

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

sequential circuits

Venkataramani, P. and Srivastava, S. and Bhanja, S. (2008) Sequential circuit design in quantum-dot cellular automata. In: Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, 18-21 Aug. 2008, Arlington, TX.

side channel attacks

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

standard CS courses

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

standard EE courses

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

students motivation

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

switching power

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

table lookup

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

tagged repair

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

tagging mechanism

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

thermal hot spots

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

thermal resistance.

Yao, Jun and Yao, Yufeng and Mason, Peter J. and Patel, Mayur K. (2009) Numerical simulation of heat transfer in rectangular microchannel. Journal of Advances in Applied Mathematics and Mechanics, 1 (2). pp. 231-241. ISSN 2070-0733

undergraduate logic design course

Srivastava, S. and Bhanja, S. (2007) Integrating nano-logic into an undergraduate logic design course. In: Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on, 3-4 June 2007, San Diego, CA.

upper bound estimation

Srivastava, S. and Sarkar, S. and Bhanja, S. (2009) Estimation of upper bound of power dissipation in QCA circuits. Nanotechnology, IEEE Transactions on, 8 (1). pp. 116-127. ISSN 1536-125X

upper bound power model

Liu, Weiqiang and Srivastava, Saket and Lu, Liang and O'Neill, M. and Swartzlander, E. E. (2012) Are QCA cryptographic circuits resistant to power analysis attack? Nanotechnology, IEEE Transactions on, 11 (6). pp. 1239-1251. ISSN 1536-125X

This list was generated on Sat Oct 25 09:29:58 2014 BST.