A 14-bit 250 MS/s IF sampling pipelined ADC in 180 nm CMOS process

Zheng, Xuqiang, Wang, Zhijun, Li, Fule , Zhao, Feng, Yue, Shigang, Zhang, Chun and Wang, Zhihua (2016) A 14-bit 250 MS/s IF sampling pipelined ADC in 180 nm CMOS process. IEEE Transactions on Circuits and Systems I: Regular Papers, 63 (9). pp. 1381-1392. ISSN 1549-8328

25371 PIPELINED ADC-FINAL VERSION-20160606.pdf - Whole Document

Item Type:Article
Item Status:Live Archive


This paper presents a 14-bit 250 MS/s ADC fabricated
in a 180 nm CMOS process, which aims at optimizing its
linearity, operating speed, and power efficiency. The implemented
ADC employs an improved SHA with parasitic optimized bootstrapped
switches to achieve high sampling linearity over a wide
input frequency range. It also explores a dedicated foreground
calibration to correct the capacitor mismatches and the gain
error of residue amplifier, where a novel configuration scheme
with little cost for analog front-end is developed. Moreover, a
partial non-overlapping clock scheme associated with a highspeed
reference buffer and fast comparators is proposed to
maximize the residue settling time. The implemented ADC is
measured under different input frequencies with a sampling rate
of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30
MHz input, the measured SFDR and SNDR of the ADC is 94.7
dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for
up to 400 MHz. The measured DNL and INL after calibration
are optimized to 0.15 LSB and 1.00 LSB, respectively, while the
Walden FOM at Nyquist frequency is 0.57 pJ/step.

Keywords:high linearity, high conversion speed, IF sampling, low-cost configuration, pipelined analog-to-digital converter, NotOAChecked
Subjects:G Mathematical and Computer Sciences > G400 Computer Science
H Engineering > H130 Computer-Aided Engineering
Divisions:College of Science > School of Computer Science
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ID Code:25371
Deposited On:13 Dec 2016 10:42

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