Meng, Hongying and Appiah, Kofi and Hunter, Andrew and Dickinson, Patrick (2011) FPGA implementation of Naive Bayes classifier for visual object recognition. In: Seventh IEEE Workshop on Embedded Computer Vision, 20-25 June 2011, Colorado Springs.
Full content URL: http://dx.doi.org/10.1109/CVPRW.2011.5981831
Full text not available from this repository.
|Item Type:||Conference or Workshop contribution (Paper)|
|Item Status:||Live Archive|
In this paper, a Naive Bayes classifier was simplified and implemented as a multi-class classification tool for binary
feature vectors. It was designed on FPGA using very limited hardware resources and runs quickly and efficiently in both training and testing phases. It was first tested on a handwriting digital number dataset, and then applied in the
visual object recognition on a single FPGA based visual surveillance system. It was compared with a binary Self Organizing Map (bSOM) using tri-states operation on FPGA, and the experimental results demonstrated both its higher
performance and lower resource usage on the FPGA chip.
|Keywords:||FPGA, Bayes Classifier, Recognition|
|Subjects:||G Mathematical and Computer Sciences > G700 Artificial Intelligence|
G Mathematical and Computer Sciences > G740 Computer Vision
|Divisions:||College of Science > School of Computer Science|
|Deposited On:||08 Apr 2011 18:18|
Repository Staff Only: item control page