Appiah, Kofi and Hunter, Andrew (2005) A single-chip FPGA implementation of real-time adaptive background model. In: IEEE 2005 Conference on Field-Programmable Technology (FPT' 05), December 11-14, 2005, National University of Singapore, Singapore.

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Abstract

This paper demonstrates the use of a single-chip FPGA for the extraction of highly accurate background models in real-time. The models are based on 24-bit RGB values and 8-bit grayscale intensity values. Three background models are presented, all using a camcorder, single FPGA chip, four blocks of RAM and a display unit. The architectures have been implemented and tested using a Panasonic NVDS60B digital video camera connected to a Celoxica RC300 Prototyping Platform with a Xilinx Virtex II XC2v6000 FPGA and 4 banks of onboard RAM. The novel FPGA architecture presented has the advantages of minimizing latency and the movement of large datasets, by conducting time critical processes on BlockRAM. The systems operate at clock rates ranging from 57MHz to 65MHz and are capable of performing pre-processing functions like temporal low-pass filtering on standard frame size of 640X480 pixels at up to 210 frames per second.

Item Type:	Conference or Workshop Item (Paper)
Additional Information:	This paper demonstrates the use of a single-chip FPGA for the extraction of highly accurate background models in real-time. The models are based on 24-bit RGB values and 8-bit grayscale intensity values. Three background models are presented, all using a camcorder, single FPGA chip, four blocks of RAM and a display unit. The architectures have been implemented and tested using a Panasonic NVDS60B digital video camera connected to a Celoxica RC300 Prototyping Platform with a Xilinx Virtex II XC2v6000 FPGA and 4 banks of onboard RAM. The novel FPGA architecture presented has the advantages of minimizing latency and the movement of large datasets, by conducting time critical processes on BlockRAM. The systems operate at clock rates ranging from 57MHz to 65MHz and are capable of performing pre-processing functions like temporal low-pass filtering on standard frame size of 640X480 pixels at up to 210 frames per second.
Keywords:	FPGA, adaptive background model
Subjects:	H Engineering > H670 Robotics and Cybernetics G Mathematical and Computer Sciences > G400 Computer Science
Divisions:	College of Sciences > Faculty of Science > Lincoln School of Computer Science
Depositing User:	Kofi Appiah
Date Deposited:	07 Jul 2010 13:52
Last Modified:	13 Mar 2013 08:41
URI:	http://eprints.lincoln.ac.uk/id/eprint/2800

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• A single-chip FPGA implementation of real-time adaptive background model. (deposited 26 Oct 2005)
  • A single-chip FPGA implementation of real-time adaptive background model. (deposited 07 Jul 2010 13:52) [Currently Displayed]

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