A binary self-organizing map and its FPGA implementation

Appiah, Kofi and Hunter, Andrew and Meng, Hongying and Yue, Shigang and Hobden, Mervyn and Priestley, Nigel and Hobden, Peter and Pettit, Cy (2009) A binary self-organizing map and its FPGA implementation. In: IEEE International Joint Conference on Neural Networks, June 14-29, 2009, Westin PeachTree Hotel, in Atlanta, Georgia.

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A binary self-organizing map and its FPGA implementation
A binary self-organizing map and its FPGA implementation
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Item Type:Conference or Workshop contribution (Paper)
Item Status:Live Archive


A binary Self Organizing Map (SOM) has been designed and
implemented on a Field Programmable Gate Array (FPGA) chip. A novel learning algorithm which takes binary inputs and maintains tri-state weights is presented. The binary SOM has the capability of recognizing binary input sequences after training. A novel tri-state rule is used in updating the network weights during the training phase. The rule implementation is highly suited to the FPGA architecture, and allows extremely rapid training. This architecture may be used in real-time for fast pattern clustering and classification of the binary features.

Keywords:FPGA, SOM, Binary Patterns
Subjects:G Mathematical and Computer Sciences > G730 Neural Computing
G Mathematical and Computer Sciences > G740 Computer Vision
Divisions:College of Science > School of Computer Science
ID Code:1852
Deposited On:23 Mar 2009 16:13

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