Appiah, Kofi and Hunter, Andrew and Dickinson, Patrick and Owens, Jonathan (2008) A run-length based connected component algorithm for FPGA implementation. In: International Conference on Field-Programmable Technology 2008, 7th - 10th December, Taipei, Taiwan .
|Item Type:||Conference or Workshop Item (Paper)|
Restricted to Registered users only
|Divisions:||College of Science > School of Computer Science|
|Abstract:||This paper introduces a real-time connected component labelling algorithm designed for Field Programmable Gate Array (FPGA) implementation. The algorithm run-length encodes the image, and performs connected component analysis on this representation. The run-length encoding, together with other parts of the algorithm, is performed in parallel; sequential operations are minimized as the number of runs is typically far less than the number of pixels. The architecture is designed mainly on Block RAM (i.e.internal RAM) of the FPGA. A comparison with the multi-pass algorithm in hardware and software is presented to show the advantages of the algorithm. The algorithm runs comfortably in real-time with reasonably low resource utilization, making integration with other real-time algorithms feasible.|
|Date Deposited:||15 Oct 2008 18:00|
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