FPGA based speeded up robust features

Svab, Jan and Krajnik, Tomas and Faigl, Jan and Preucil, Libor (2009) FPGA based speeded up robust features. In: IEEE International Conference on Technologies for Practical Robot Applications (TePRA 2009), 9-10 November 2009, Woburn, MA, USA.

Full content URL: http://dx.doi.org/10.1109/TEPRA.2009.5339646

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FPGA based speeded up robust features
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Item Type:Conference or Workshop contribution (Paper)
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Abstract

We present an implementation of the Speeded Up Robust Features (SURF) on a Field Programmable Gate Array (FPGA). The SURF algorithm extracts salient points from image and computes descriptors of their surroundings that are invariant to scale, rotation and illumination changes. The interest point detection and feature descriptor extraction algorithm is often used as the first stage in autonomous robot navigation, object recognition and tracking etc. However, detection and extraction are computationally demanding and therefore can't be used in systems with limited computational power. We took advantage of algorithm's natural parallelism and implemented it's most demanding parts in FPGA logic. Several modifications of the original algorithm have been made to increase it's suitability for FPGA implementation. Experiments show, that the FPGA implementation is comparable in terms of precision, speed and repeatability, but outperforms the CPU and GPU implementation in terms of power consumption. Our implementation is intended to be used in embedded systems which are limited in computational power or as the first stage preprocessing block, which allows the computational resources to focus on higher level algorithms.

Keywords:Field programmable gate arrays (FPGA), Computer vision
Subjects:H Engineering > H670 Robotics and Cybernetics
G Mathematical and Computer Sciences > G740 Computer Vision
Divisions:College of Science > School of Computer Science
ID Code:14903
Deposited On:12 Sep 2014 09:21

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