Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2009) Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. In: Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, 30-31 July 2009, San Francisco, CA.

Full content URL: http://dx.doi.org/10.1109/NANOARCH.2009.5226354

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Abstract

In this paper we propose two efficient repair techniques for hybrid nano/CMOS architecture to provide high level of defect tolerance at a modest cost. We have applied the proposed techniques to a lookup table(LUT) based Boolean logic approach. The proposed repair techniques are efficient in utilization of spare units and viable for various Boolean logic implementations. We show that the proposed techniques are capable of handling upto 20 defect rates in hybrid nano/CMOS architecture and upto 14 defect rates for large ISCAS'85 benchmark circuits synthesized into smaller sized LUTs.

Keywords:Boolean functions, CMOS logic circuits, nanoelectronics, network synthesis, table lookup, ISCAS'85 benchmark circuit synthesis, LUT-based Boolean logic approach, defect tolerance, hybrid nanoCMOS architecture, lookup table, repair technique, tagging mechanism, Application software, Automatic control, Automation, Computer aided instruction, Computer science, Computer science education, Educational technology, Instruments, Military computing, Tagging
Subjects:H Engineering > H611 Microelectronic Engineering
H Engineering > H610 Electronic Engineering
H Engineering > H612 Integrated Circuit Design
Divisions:College of Science > School of Computer Science
College of Science > School of Engineering
ID Code:10743
Deposited On:26 Jul 2013 09:00

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