Fault-tolerance techniques for hybrid CMOS/nanoarchitecture

Melouki, Aissa and Srivastava, Saket and Al-Hashimi, Bashir M. (2010) Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. Computers Digital Techniques, IET, 4 (3). pp. 240-250. ISSN 1751-8601

Full content URL: http://dx.doi.org/10.1049/iet-cdt.2008.0146

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Abstract

The authors propose two fault-tolerance techniques for hybrid CMOS/nanoarchitecture implementing logic functions as look-up tables. The authors compare the efficiency of the proposed techniques with recently reported methods that use single coding schemes in tolerating high fault rates in nanoscale fabrics. Both proposed techniques are based on error correcting codes to tackle different fault rates. In the first technique, the authors implement a combined two-dimensional coding scheme using Hamming and Bose-Chaudhuri-Hocquenghem (BCH) codes to address fault rates greater than 5. In the second technique, Hamming coding is complemented with bad line exclusion technique to tolerate fault rates higher than the first proposed technique (up to 20). The authors have also estimated the improvement that can be achieved in the circuit reliability in the presence of Don-t Care Conditions. The area, latency and energy costs of the proposed techniques were also estimated in the CMOS domain.

Keywords:BCH codes, CMOS logic circuits, Hamming codes, error correction codes, fault tolerance, integrated circuit reliability, table lookup, Bose Chaudhuri Hocquenghem codes, bad line exclusion technique, circuit reliability, don't care conditions, error correcting codes, fault rate tolerance techniques, hybrid CMOS-nanoarchitecture, logic functions, look-up tables
Subjects:H Engineering > H611 Microelectronic Engineering
H Engineering > H610 Electronic Engineering
H Engineering > H612 Integrated Circuit Design
Divisions:College of Science > School of Computer Science
College of Science > School of Engineering
ID Code:10741
Deposited On:17 Jul 2013 14:09

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