Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture

Srivastava, S. and Melouki, A. and Al-Hashimi, B. M. (2011) Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture. Nanotechnology, IEEE Transactions on, 10 (3). pp. 424-432. ISSN 1536-125X

Full content URL: http://dx.doi.org/10.1109/TNANO.2010.2045393

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Abstract

We propose two new repair techniques for hybrid nano/CMOS computing architecture with lookup-table-based Boolean logic. Our proposed techniques use tagging mechanism to provide high level of defect tolerance, and we present theoretical equations to predict the repair capability, including an estimate of the repair cost. The repair techniques are efficient in utilization of spare units and capable of targeting up to 20 defect rates, which is higher than recently reported repair techniques.

Additional Information:Date of [online] publication March 18th 2010
Keywords:Boolean functions, CMOS integrated circuits, identification technology, nanoelectronics, table lookup, Boolean logic, defect tolerance, hybrid nano/CMOS computing architecture, lookup-table, tagged repair, CMOS logic circuits, CMOS technology, Computer architecture, Computer science, Fault tolerance, Logic functions, Manufacturing, Permission, hybrid nano/CMOS, reliability, repair techniques
Subjects:H Engineering > H611 Microelectronic Engineering
G Mathematical and Computer Sciences > G411 Computer Architectures
G Mathematical and Computer Sciences > G400 Computer Science
H Engineering > H610 Electronic Engineering
H Engineering > H612 Integrated Circuit Design
Divisions:College of Science > School of Computer Science
College of Science > School of Engineering
ID Code:10735
Deposited On:16 Jul 2013 08:00

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